Semiconductor memory device, controller, and memory system

ABSTRACT

Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2018-0127276, filed on Oct. 24, 2018, and KoreanPatent Application No. 10-2018-0134888, filed on Nov. 6, 2018, thedisclosure of each of which is incorporated herein by reference in itsentirety.

BACKGROUND 1. Field

Devices, controllers, and systems consistent with example embodimentsrelate to a semiconductor memory device, a controller, and a memorysystem.

2. Description of Related Art

A memory system may include a semiconductor memory device and acontroller. Generally, each of a semiconductor memory device and acontroller may perform a predetermined error correcting code (ECC)decoding operation. For example, the semiconductor memory device mayperform a 1-bit error detection and 1-bit error correction operation andthe controller may perform only a 3-bit error detection operation oronly a 1-bit error correction and 2-bit error detection operation.However, it is desired that the controller performs a different ECCdecoding operation according to a type of an error.

SUMMARY

The example embodiments of the inventive concept are directed toproviding a semiconductor memory device, a controller, and a memorysystem capable of generating a decoding status flag (DSF) according to atype of an error and selectively performing a different error correctioncode decoding operation on the basis of the decoding status flag.

The scope of the inventive concept is not limited to the above-describedobject, and other unmentioned objects may be clearly understood by thoseskilled in the art from the following descriptions.

According to example embodiments, there is provided a semiconductormemory device which includes a row decoder configured to decode a rowaddress to generate a word line selection signal, a column decoderconfigured to decode a column address to generate a column selectionsignal, a memory cell array including a plurality of memory cells, oneor more memory cells are selected in response to the word line selectionsignal and the column selection signal, and an error correcting code(ECC) decoder configured to receive first data and a parity output fromselected memory cells of the memory cell array and generate a syndromebased on the first data and the parity. In response to a read operationof the semiconductor memory device being performed, the ECC decodergenerates second data and a decoding status flag (DSF) indicating a typeof an error of the first data by the syndrome and outputs the seconddata and the DSF to an external device outside of the semiconductormemory device. A number of bits of the first data may be the same as anumber of bits of the second data.

According to example embodiments, there is provided a controller whichincludes an ECC decoder configured to perform an ECC decoding operationselected from among a plurality of ECC decoding operations on first dataapplied from an external device outside of the controller in response toa decoding status flag (DSF) applied from the external device andindicating a type of an error of the first data and generate second dataand an error signal by performing the selected ECC decoding operation.

According to example embodiments, there is provided a memory systemwhich includes a semiconductor memory device including a row decoderconfigured to decode a row address to generate a word line selectionsignal, a column decoder configured to decode a column address togenerate a column selection signal, a memory cell array including aplurality of memory cells, one or more memory cells are selected inresponse to the word line selection signal and the column selectionsignal, and including a first ECC decoder configured to perform a firstECC decoding operation by receiving first data and a parity output fromselected memory cells of the memory cell array, to generate a syndromebased on the first data and the parity, to generate second data byperforming the first ECC decoding operation, and to generate a decodingstatus flag (DSF) indicating a type of an error of the first data by thesyndrome when a read operation of the semiconductor memory device isperformed. The memory system further includes a controller configured tocontrol the semiconductor memory device. The controller includes asecond ECC decoder configured to perform an ECC decoding operationselected from among a plurality of ECC decoding operations on the seconddata applied from the semiconductor memory device in response to the DSFapplied from the semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a semiconductor memory device according toan example embodiment of the inventive concept.

FIG. 2 is a diagram showing an error correcting code (ECC) encoderaccording to an example embodiment of the inventive concept.

FIG. 3 is a diagram for describing a parity operation of a first paritygenerator according to an example embodiment of the inventive concept.

FIG. 4 is a diagram showing a configuration of an ECC decoder accordingto an example embodiment of the inventive concept.

FIG. 5 is a diagram for describing a syndrome operation of a firstsyndrome generator according to an example embodiment of the inventiveconcept.

FIG. 6 is a block diagram showing a memory system according to anexample embodiment of the inventive concept.

FIG. 7 is a block diagram showing a configuration of an ECC decoderaccording to an example embodiment of the inventive concept.

FIG. 8 is a diagram showing a first ECC decoding unit according to anexample embodiment of the inventive concept.

FIG. 9 is a diagram for describing a syndrome operation of a secondsyndrome generator according to an example embodiment of the inventiveconcept.

FIG. 10 is a diagram showing a second ECC decoding unit according to anexample embodiment of the inventive concept.

FIG. 11 is a block diagram showing a configuration of an ECC decoderaccording to an example embodiment of the inventive concept.

DETAILED DESCRIPTION

Hereinafter, a semiconductor memory device, a controller, and a memorysystem according to example embodiments of the inventive concept will bedescribed with reference to the accompanying drawings.

FIG. 1 is a block diagram of a semiconductor memory device according toan example embodiment of the inventive concept, and a semiconductormemory device 100 may include a command and address generator 10, a rowaddress generator 12, a column address generator 14, a row decoder 16, acolumn decoder 18, a memory cell array 20, a first error correcting code(ECC) encoder 22, a first ECC decoder 24, a data write path unit 26, anda data read path unit 28. As used herein, a “unit” and a “block” may beimplemented by a circuit, such as part of an integrated circuit of thesemiconductor memory device.

A function of each of the blocks shown in FIG. 1 will be described asfollows.

The command and address generator 10 may decode a command signalincluded in a command and address CA to generate an active command ACT,a write command WR, or a read command RD and may generate a row addressRADD or a column address CADD from an address signal included in thecommand and address CA. The row address RADD may be generated togetherwith the active command ACT, and the column address CADD may begenerated together with the write command WR or the read command RD.

The row address generator 12 may receive the row address RADD togenerate a row address signal ra.

The column address generator 14 may receive the column address CADD togenerate a column address signal ca.

The row decoder 16 may decode the row address signal ra to generate aplurality of word line selection signals wl.

The column decoder 18 may decode the column address signal ca togenerate a plurality of column selection signals csl.

The memory cell array 20 may include a plurality of memory cells (notshown), store data and parity of data di in memory cells which areselected by one of the plurality of word line selection signals wl andone of the plurality of column selection signals csl when a writeoperation is performed in response to the write command WR, and outputdata and parity of data do from selected memory cells when a readoperation is performed in response to the read command RD. For example,the memory cell array 20 may store or output 16n-bit data and j-bitparity of data di or data do. Here, each of n and j is a natural numberequal to or greater than 1. In example embodiments, a number of bits ofthe 16n-bit data may be variable such as bits of 4n-bit, bits of 8n-bit,bits of 32n-bit, etc.

The first ECC encoder 22 may receive data DI to generate a parity of thedata DI and output the data and the parity as data di. For example, thefirst ECC encoder 22 may generate 16n-bit data and j-bit parity for the16n-bit data as the data di. As an example, the 16n-bit data DI mayinclude x-bit data and y-bit parity. As another example, the 16n-bitdata DI may include x-bit data, y-bit parity and z-bit dummy data.

The first ECC decoder 24 may receive data do including 16n-bit data andj-bit parity from selected memory cells to generate a syndrome andgenerate a decoding status flag (DSF) on the basis of a type of an errorusing the syndrome. For example, the number of bits of the syndrome maybe predetermined as the parity. For example, a number of bits of thedata di may be equal to the number of bits of the data do. Here, thetype of an error may be a non-error NE, a correctable error CE, or anuncorrectable error UE. As used herein, “non-error” indicates that datahas no error bit. For example, the first ECC decoder 24 may generate aDSF by setting the DSF to “0” in the case of the non-error NE or thecorrectable error CE and setting the DSF to “1” in the case of theuncorrectable error UE. The first ECC decoder 24 may generate 16n-bitdata of data DO and a 1-bit DSF in series or in parallel. The first ECCdecoder 24 may correct an error included in the 16n-bit data and thej-bit parity of the data do and generate the 16n-bit data of data DO andthe DSF of “0” in the case of the correctable error CE, for example, a1-bit error.

The semiconductor memory device 100 may include an ECC engine (or, anECC circuit) configured to perform an ECC decoding operation and an ECCencoding operation. The ECC engine may include the first ECC encoder 22and the first ECC decoder 24.

The data write path unit 26 may sequentially receive data DQ in seriesand output the data DQ as data DI in parallel. For example, the datawrite path unit 26 may receive n-bit data 16 times in series to generate16n-bit data. The data write path unit 26 may receive data DQ and outputthe data DQ as data DI when the semiconductor memory device 100 performsa write operation.

The data read path unit 28 may receive data DO and sequentially outputthe data DO in series. For example, the data read path unit 28 mayreceive 16n-bit data in parallel to output the n-bit data 16 times inseries. Further, the data read path unit 28 may transmit a 1-bit DSF inseries through one among data terminals (not shown) for transmittingn-bit data, or transmit the 1-bit DSF in parallel to n-bit data througha separate terminal (not shown). In other example, the data read pathunit 28 may transmit at least two-bit DSF. The data read path unit 28may receive data DO and output the data DO as the data DQ when thesemiconductor memory device 100 performs a read operation.

Although not shown, the semiconductor memory device 100 according toexample embodiments of the inventive concept may have a burst length(BL) set to 16 and sequentially receive or output the n-bit data 16times in series through n data terminals (not shown).

FIG. 2 is a diagram showing the first ECC encoder 22 according to theexample embodiment of the inventive concept, and the first ECC encoder22 may include a first parity generator 32.

Referring to FIG. 2, the first parity generator 32 may receive the dataDI applied from the data write path unit 26 to generate data and parityof the data di. For example, the first parity generator 32 may generatej-bit parity using a first H matrix and the 16n-bit data.

FIG. 3 is a diagram for describing a parity operation of the firstparity generator 32 according to the example embodiment of the inventiveconcept, which is for describing the parity operation in the case inwhich each of n and j is eight.

Referring to FIG. 3, a first H matrix H may be an 8×136 matrix, and amatrix R of 128-bit data and 8-bit first parity may be a 136×1 matrix.In the first H matrix H, codes (h11 to h81, h12 to h82, . . . , andh1128 to h8128, 10 . . . 0, 01 . . . 0, . . . , and 00 . . . 1) of 136column vectors C1 to C136 may have different codes including “0” and “1”except for a code including all “0.” Further, for the first H matrix H,a total of 2¹²⁸ different codes including the codes (h11 to h1128, h21to h2128, . . . , and h81 to h8128) of row vectors R1 to R8 may begenerated, and the same or different 8-bit parity for each of the 2¹²⁸codes in total may be generated. In this case, a minimum Hammingdistance (dmin) between any two codes of the 2¹²⁸ different 136-bitcodes in total may be three.

Referring to FIGS. 2 and 3, the first parity generator 32 may perform anexclusive OR (XOR) operation on each of the codes (h11 to h1128, h21 toh2128, . . . , and h81 to h8128) included in the row vectors R1 to R8 ofthe first H matrix H and 128-bit data (r1 to r128) of the 136×1 matrixand then perform a modulo 2 operation thereon to generate 8-bit parityP21 to P21.

That is, the 8-bit parity P21 to P28 may be expressed by the followingequations.

P21=h11{circumflex over ( )}r1+h12{circumflex over ( )}r2+ . . .+h1128{circumflex over ( )}r128

P22=h21{circumflex over ( )}r1+h22{circumflex over ( )}r2+ . . .+h2128{circumflex over ( )}r128

. . .

P28=h81{circumflex over ( )}r1+h82{circumflex over ( )}r2+ . . .+h8128{circumflex over ( )}r128

In the above equations, “{circumflex over ( )}” denotes an XOR operatorand “+” denotes a modulo 2 operator.

FIG. 4 is a diagram showing a configuration of the first ECC decoder 24according to the example embodiment of the inventive concept, and thefirst ECC decoder 24 may include a first syndrome generator 24-2, afirst error detector 24-3, a DSF generator 24-4, a first error positiondetector 24-5, a first error corrector 24-6, and a first switch SW1.

A function of each of the blocks shown in FIG. 4 will be described asfollows. The first syndrome generator 24-2 may receive 16n-bit data andj-bit parity of the data do which are output from the memory cell array20 to generate a j-bit syndrome. For example, each of n and j may beeight, and the first syndrome generator 24-2 may perform an XORoperation on each of row vectors of the first H matrix, that is, an8×136 matrix, and a 136×1 matrix of 136-bit data, and then perform amodulo 2 operation thereon to generate an 8-bit syndrome.

FIG. 5 is a diagram for describing a syndrome operation of the firstsyndrome generator 24-2 according to the example embodiment of theinventive concept, which is for describing the syndrome operation in thecase in which each of n and j is eight.

Referring to FIG. 5, a second H matrix H′ may be an 8×136 matrix, and amatrix R′ of 128-bit data and 8-bit parity of the data do may be a 136×1matrix. Codes (h11′ to h81′, h12′ to h82′, . . . , and h1136′ to h8136′)of 136 column vectors C1′ to C136′ may have different codes including“0” and “1” except for a code including all “0.” In the second H matrixH′, a total of 2¹²⁸ different codes including the codes (h11′ to h1128′,h21′ to h2128′, . . . , and h81′ to h8128′) of row vectors R1′ to R8′may be generated, and the same or different 8-bit second parity for eachof the 2¹²⁸ codes in total may be generated. In this case, a minimumHamming distance (dmin) between any two codes of the 2¹²⁸ different136-bit codes in total may be three. For example, the first ECC decoder24 shown in FIG. 1 may perform a 1-bit error correction and 1-bit errordetection operation.

Referring to FIGS. 4 and 5, the first syndrome generator 24-2 mayperform an XOR operation on each of the codes (h11′ to h1136′, h21 toh2136′, . . . , and h81 to h8136′) of the row vectors R1′ to R8′ of thesecond H matrix H′ and a code (r1′ to r128′ and P1′ to P8′) of the 136×1matrix and then perform a modulo 2 operation thereon to generate an8-bit syndrome (S1 to S8).

That is, the 8-bit syndrome (S1 to S8) may be expressed by the followingexpressions.

S1=h11′{circumflex over ( )}r1′+h12′{circumflex over ( )}r2′+ . . .+h1128′{circumflex over ( )}r128′+ . . . +h1136′{circumflex over ( )}P8′

S2=h21′{circumflex over ( )}r1′+h22′{circumflex over ( )}r2′+ . . .+h2128′{circumflex over ( )}r128′+ . . . +h2136′{circumflex over ( )}P8′

. . .

S8=h81′{circumflex over ( )}r1′+h82′{circumflex over ( )}r2′+ . . .+h8128′{circumflex over ( )}r128′+ . . . +h8136′{circumflex over ( )}P8′

In the above expressions, “{circumflex over ( )}” denotes an XORoperator and “+” denotes a modulo 2 operator.

Referring to FIG. 4, the first error detector 24-3 may generate anon-error signal ne indicating a non-error NE when the 8-bit syndrome(S1 to S8) is all “0,” generate a correctable error signal ce indicatinga correctable error CE as a 1-bit error when the 8-bit syndrome (S1 toS8) is included in the codes of the 136 column vectors C1′ to C136′ ofthe second H matrix H′, or generate an uncorrectable error signal ueindicating an uncorrectable error UE when the 8-bit syndrome (S1 to S8)is not present in the codes of the 136 column vectors C1′ to C136′ ofthe second H matrix H′.

Referring to FIG. 4, the DSF generator 24-4 may generate a DSF of afirst state, for example, a DSF of “0,” when the non-error signal ne orthe correctable error signal ce is generated and generate a DSF of asecond state, for example, a DSF of “1,” when the uncorrectable errorsignal ue is generated. For example, the DSF generator 24-4 may generatethe DSF of “0,” or “1” based on a type of error such as a non-error NE,a correctable error CE and an uncorrectable error UE. The DSF generator24-4 may output the DSF of “0,” or “1” to an external device (e.g., acontroller 110 as shown in FIG. 6) outside of the semiconductor memorydevice 100 when the semiconductor memory device 100 performs a readoperation. For example, the DSF generator 24-4 may output the DSFthrough one of data terminals (e.g., data pads or data pins) of data DQwith data or through a separate terminal (e.g., a pad or a pin) otherthan the data terminals.

Referring to FIG. 4, the first error position detector 24-5 may detectan error position by checking a position of the column vector, of whichcodes among the codes of the 136 column vectors C1′ to C136′ of thesecond H matrix H′ match the 8-bit syndrome (S1 to S8) in response tothe correctable error signal ce, and generate error positioninformation. For example, the first error position detector 24-5 maygenerate the error position information indicating that there is anerror at a first position when the 8-bit syndrome (S1 to S8) match thecodes of a first column vector C1′ of the second H matrix H′.

Referring to FIG. 4, the first error corrector 24-6 may correct an errorof (16n+j)-bit data on the basis of the error position information. Forexample, the first error corrector 24-6 may correct the error byinverting a first bit r1′ (shown in FIG. 5) of the code (r1′ to r128′and P1′ to P8′) of the 136×1 matrix when the error position informationindicates that the error is at the first position. The first errorcorrector 24-6 may generate 16n-bit data excluding a j-bit parityincluded in the corrected (16n+j)-bit data of the data do as the dataDO.

Referring to FIG. 4, the first switch SW1 may be turned on in responseto the non-error signal ne (or the uncorrectable error signal ue) togenerate the 16n-bit data as the data DO.

FIG. 6 is a block diagram showing a memory system according to anexample embodiment of the inventive concept, and a memory system 200 mayinclude a semiconductor memory device 100 and a controller 110. Thecontroller 110 may include a second ECC encoder 112, a second ECCdecoder 114, and a data processing unit 116 (such as a micro-processor,a central processing unit CPU, etc.). In other example embodiments, thedata processing unit 116 may be separate from the controller 110. Forexample, the memory system 200 may include the semiconductor memorydevice 100, the controller 110 and the data processing unit 116.

A function of each of the blocks shown in FIG. 6 will be described asfollows.

The semiconductor memory device 100 may receive a command and address CAand data DQ from the controller 110, and output data DQ and a DSF to thecontroller 110. Unlike what is shown in the drawing, the DSF may betransmitted before, during, or after the transmission of the data DQthrough one of data terminals (not shown) through which the data DQ istransmitted, rather than a separate terminal. For example, the DSF maybe transmitted through a terminal (not shown) separated from the dataterminals.

The controller 110 may output the command and address CA and the data DQto the semiconductor memory device 100, and receive the data DQ and theDSF from the semiconductor memory device 100.

The second ECC encoder 112 may receive x-bit data DO′ to generate y-bitparity of the x-bit data DO′, and output 16n-bit data (wherein 16n=x+y).For example, the 16n-bit data may include the x-bit data DO′ and they-bit parity. For example, x may be 120, and y may be 8.

The second ECC decoder 114 may receive the data DQ of 16n-bit data andthe DSF from the semiconductor memory device 100 to perform an ECCdecoding operation selected from among a plurality of ECC decodingoperations in response to the DSF, and generate data DI′ and an errorsignal E. For example, the second ECC decoder 114 may perform a firstECC decoding operation when the DSF is “0” and perform a second ECCdecoding operation when the DSF is “1.”

In example embodiments, the first ECC decoding operation may be a 3-biterror detection operation and the second ECC decoding operation may be a1-bit error correction and 2-bit error detection operation.

In example embodiments, the selected ECC decoding operation may be ap-bit error detection operation or q-bit error correction and (q+1)-biterror detection operation. Here, p is natural number equal to or greaterthan 4 and q is a natural number greater than 2.

The controller 110 may include an ECC engine (or, an ECC circuit)configured to perform an ECC decoding operation and an ECC encodingoperation. The ECC engine may include the second ECC encoder 112 and thesecond ECC decoder 114. Each of the 3-bit error detection operation andthe 1-bit error correction and 2-bit error detection operation may bereferred to as a decoding rule of the ECC engine of the memory system200.

The data processing unit 116 may generate the x-bit data DO′ and receivethe x-bit data DI′ and the error signal E to perform a data processingoperation for the x-bit data DI′.

When the first error detector 24-3 shown in FIG. 4 determines that theerror is a 1-bit error and generates the correctable error signal ce, itmeans that the 1-bit error is substantially generated. However, in somecases, it means that a 2-bit error is substantially generated ratherthan the 1-bit error. For example, it is determined that the 1-bit erroris generated because the j-bit syndrome matches the code of one columnvector among the column vectors C1′ to C136′ of the second H matrix H′,for example, the code of the first column vector. However,substantially, the error may be a 2-bit error which is generated by anXOR operation of the 8-bit syndrome (S1 to S8) and the codes ofdifferent two column vectors. Miscorrection in which the first errorcorrector 24-6 shown in FIG. 4 inverts the first bit r1′ (shown in FIG.5) of the 16n-bit data to correct the error may be performed. As aresult, an error may be generated in 3 bits of the 16n-bit data andtransmitted. The DSF generator 24-4 shown in FIG. 4 may transmit the DSFof “0.” In this case, the second ECC decoder 114 shown in FIG. 6 mayperform a 3-bit error detection operation to detect the miscorrection.Therefore, the second ECC decoder 114 may perform the 3-bit errordetection operation to detect the miscorrection when the type of theerror is the non-error NE or the correctable error CE and may performthe 1-bit error correction and 2-bit error detection operation tocorrect the 1-bit error when the type of the error is the uncorrectableerror UE, and thus may selectively and efficiently perform the ECCdecoding operation.

FIG. 7 is a block diagram showing a configuration of the second ECCdecoder 114 according to the example embodiment of the inventiveconcept, and the second ECC decoder 114 may include a first selector114-2, a first ECC decoding unit 114-4, a second ECC decoding unit114-6, and a second selector 114-8.

A function of each of the blocks shown in FIG. 7 will be described asfollows.

The first selector 114-2 may receive data DQ in response to a DSF tooutput the data DQ to the first ECC decoding unit 114-4 or the secondECC decoding unit 114-6. For example, the first selector 114-2 mayoutput 16n-bit data to the first ECC decoding unit 114-4 when the DSF is“0” and output the 16n-bit data to the second ECC decoding unit 114-6when the DSF is “1.”

The first ECC decoding unit 114-4 may receive the 16n-bit data, performa 3-bit error detection operation, and generate x-bit first data D1 anda first error signal E1.

The second ECC decoding unit 114-6 may receive the 16n-bit data, performa 1-bit error correction and 2-bit error detection operation, andgenerate x-bit second data D2 and a second error signal E2.

In example embodiments, the second ECC decoder 114 may perform either afirst ECC decoding operation by the first ECC decoding unit 114-4 or asecond ECC decoding operation by the second ECC decoding unit 114-6 inresponse to the DSF. For example, the first ECC decoding unit 114-4 mayperform the first ECC decoding operation in response to the DSF of “0,”and the second ECC decoding unit 114-6 may perform the second ECCdecoding operation in response to the DSF of “1.” The second selector114-8 may select the x-bit first data D1 and the first error signal E1or the x-bit second data D2 and the second error signal E2, which aretransmitted from the first ECC decoding unit 114-4 or the second ECCdecoding unit 114-6, in response to the DSF, and output the x-bit firstdata D1 and the first error signal E1 or the x-bit second data D2 andthe second error signal E2 as the x-bit data DI′ and the error signal E.For example, the second selector 114-8 may select and transmit the x-bitfirst data D1 and the first error signal E1 when the DSF is “0” andselect and transmit the x-bit second data D2 and the second error signalE2 when the DSF is “1.”

In example embodiments, the second ECC decoder 114 may include the firstECC decoding unit 114-4, the second ECC decoding unit 114-6, and thesecond selector 114-8 without the first selector 114-2. In this case,the first ECC decoding unit 114-4 and the second ECC decoding unit 114-6may receive the same 16n-bit data and perform the 3-bit error detectionoperation and the 1-bit error correction and 2-bit error detectionoperation, respectively, in response to the DSF.

In example embodiments, the second ECC decoder 114 may include three ormore ECC decoding units each configured to perform one of the three ormore ECC decoding operations based on the DSF. In this case, a number ofbits of the DSF may be 2 bits or more bits.

FIG. 8 is a diagram showing the first ECC decoding unit 114-4 accordingto the example embodiment of the inventive concept, and the first ECCdecoding unit 114-4 may include a second syndrome generator 114-42, asecond error detector 114-44, and a second switch SW2.

A function of each of the blocks shown in FIG. 8 will be described asfollows.

The second syndrome generator 114-42 may receive 16n-bit data DQ togenerate a y-bit syndrome for the 16n-bit data DQ. Each of n and y maybe eight, and the second syndrome generator 114-42 may perform an XORoperation on each of the row vectors of the third H matrix, that is, an8×128 matrix, and a 128×1 matrix of 128-bit data, and then perform amodulo 2 operation thereon to generate an 8-bit syndrome.

FIG. 9 is a diagram for describing a syndrome operation of the secondsyndrome generator 114-42 according to the example embodiment of theinventive concept, which is for describing the syndrome operation in thecase in which each of n and y is eight.

A third H matrix H″ may be an 8×128 matrix, and a matrix R″ of the16n-bit data DQ may be a 128×1 matrix. Codes (h11″ to h81″, h12″ toh82″, . . . , and h1128″ to h8128″) of 128 column vectors C1″ to C128″may have different codes including “0” and “1” except for a codeincluding all “0.” The codes (h81″ to h8128″) of the last row vector R8″among the row vectors R1″ to R8″ of the third H matrix H″ may be all“1.” Further, in the third H matrix H″, a total of 2¹²⁰ different codesincluding codes corresponding to 120-bit data except for an 8-bit parityamong the codes of the row vectors R1″ to R8″ may be generated, and thesame or different 8-bit second parity for each of the 2¹²⁰ codes intotal may be generated. In this case, a minimum Hamming distance (dmin)between any two codes of the 2¹²⁰ different 128-bit codes in total maybe four.

Referring to FIGS. 8 and 9, the second syndrome generator 114-42 mayperform an XOR operation on each of the codes (h11″ to h1128″, h21″ toh2128″, . . . , and h81″ to h8128″) of the row vectors R1″ to R8″ of thethird H matrix H″ and the codes (r1″ to r128″) of the 128×1 matrix andthen perform a modulo 2 operation thereon to generate an 8-bit syndrome(S1″ to S8″).

That is, the 8-bit syndrome (S1″ to S8″) may be expressed by thefollowing expressions.

S1″=h11″{circumflex over ( )}r1″+h12″{circumflex over ( )}r2″+ . . .+h1128″{circumflex over ( )}r128″

S2″=h21″{circumflex over ( )}r1″+h22″{circumflex over ( )}r2″+ . . .+h2128″{circumflex over ( )}r128″

. . .

S8″=h81″{circumflex over ( )}r1″+h82″{circumflex over ( )}r2″+ . . .+h8128″{circumflex over ( )}r128″

In the above expressions, “{circumflex over ( )}” denotes an XORoperator and “+” denotes a modulo 2 operator.

Referring to FIG. 8, the second error detector 114-44 may generate anon-error signal ne indicating a non-error NE when the 8-bit syndrome(S1″ to S8″) is all “0” and detect a 3-bit or less error including a1-bit error, a 2-bit error, or a 3-bit error when the 8-bit syndrome(S1″ to S8″) is included in the codes of 128 column vectors C1″ to C128″of the third H matrix H″ to generate a first error signal E1.

The second syndrome generator 114-42 and the second error detector114-44 may operate when the DSF is “0.”

Referring to FIG. 8, the second switch SW2 may be turned on in responseto the non-error signal ne to generate x-bit data as first data D1except for the y-bit parity included in the 16n-bit data DQ. Althoughnot shown, when the first error signal E1 is generated, the secondswitch SW2 may be configured to either transmit or not transmit thex-bit data DQ.

Although not shown, the first ECC decoding unit 114-4 may include aswitch SW2-1 disposed at node A. For example, the switch SW2-1 may beturned on in response to the DSF of “0” to electrically connect the16n-bit data DQ to the second switch SW2 and the second syndromegenerator 114-42. In this case, x-bit data of the 16n-bit data DQ may beconnected to the second switch SW2.

FIG. 10 is a diagram showing the second ECC decoding unit 114-6according to the example embodiment of the inventive concept, and thesecond ECC decoding unit 114-6 may include a third syndrome generator114-62, a third error detector 114-64, a second error position detector114-66, a second error corrector 114-68, and a third switch SW3.

A function of each of the blocks shown in FIG. 10 will be described asfollows.

The third syndrome generator 114-62 may perform the same operation asthat of the second syndrome generator 114-42 shown in FIG. 8 to generatethe y-bit syndrome of the 16n-bit data DQ.

The third error detector 114-64 may generate a non-error signal neindicating a non-error NE when the 8-bit syndrome (S1″ to S8″) is all“0” or detect a 2-bit or less error including a 1-bit error or a 2-biterror when the 8-bit syndrome (S1″ to S8″) is included in the codes ofthe 128 column vectors C1″ to C128″ of the third H matrix H″ to generatea second error signal E2.

The second error position detector 114-66 may detect an error positionby checking a position of the column vector of which codes among thecodes of the column vectors C1″ to C128″ of the third H matrix H″ matchthe 8-bit syndrome (S1″ to S8″) in response to the second error signalE2 and generate error position information. For example, the seconderror position detector 114-66 may generate the error positioninformation indicating that there is an error at a first position whenthe 8-bit syndrome (S1″ to S8″) matches the code of a first columnvector C1″ of the third H matrix H.″

The second error corrector 114-68 may correct an error of 16n-bit dataDQ on the basis of the error position information to generate seconddata D2. For example, the second error corrector 114-68 may correct theerror by inverting a first bit r1″ (shown in FIG. 9) of the 16n-bit dataDQ when the error position information indicates that the error is atthe first position and generate x-bit data excluding a y-bit parityincluded in the 16n-bit data DQ as the second data D2.

The third switch SW3 may be turned on in response to the non-errorsignal ne to transmit the x-bit data excluding the y-bit parity includedin the 16n-bit data DQ as the second data D2.

Although not shown, the second ECC decoding unit 114-6 may include aswitch SW3-1 disposed at node B. For example, the switch SW3-1 may beturned on in response to the DSF to electrically connect x-bit data ofthe 16n-bit data DQ to the third switch SW3 and the 16n-bit data to thesecond error corrector 114-68 and the third syndrome generator 114-62.

FIG. 11 is a block diagram showing a configuration of a second ECCdecoder 114′ according to other example embodiments of the inventiveconcept, and the second ECC decoder 114′ may include a fourth syndromegenerator 114-82, a fourth error detector 114-84, a third error positiondetector 114-86, a third error corrector 114-88, a fourth switch SW4,and a fifth switch SW5.

A function of each of the blocks shown in FIG. 11 will be described asfollows.

The fourth syndrome generator 114-82 and the fourth error detector114-84 may perform the same operations as those of the second syndromegenerator 114-42 and the second error detector 114-44 shown in FIG. 8,respectively.

The fourth switch SW4 may be turned on when the DSF is “1” to transmitan error signal E.

The third error position detector 114-86 may perform the same operationas that of the second error position detector 114-66 shown in FIG. 10 inresponse to the error signal E transmitted through the fourth switchSW4.

The third error corrector 114-88 may perform the same operation as thatof the second error corrector 114-68 shown in FIG. 10 in response to theerror signal E transmitted through the fourth switch SW4.

The fifth switch SW5 may be turned on in response to the non-errorsignal ne to generate x-bit data excluding the y-bit parity included inthe 16n-bit data DQ as data DI.

Unlike the second ECC decoder 114 shown in FIG. 7, in the second ECCdecoder 114′ shown in FIG. 11, the fourth syndrome generator 114-82 andthe fourth error detector 114-84 may perform a common operation when theDSF is “0” and “1.” Therefore, the second ECC decoder 114′ shown in FIG.11 may be simplified in circuit configuration as compared to the secondECC decoder 114 shown in FIGS. 7, 8, and 10.

In the above-described example embodiments, the 16n bits may berepresented by m bits (m being a natural number greater than 2).Further, in the above-described example embodiments, the DSF generator24-4 shown in FIG. 4 is described as generating the DSF of “0” when thenon-error signal ne or the correctable error signal ce is generated andis described as generating the DSF of “1” when the uncorrectable errorsignal ue is generated. However, as an example, the DSF generator 24-4may generate the DSF of “0” when the non-error signal ne is generatedand generate the DSF of “1” when the correctable error signal ce or theuncorrectable error signal ue is generated. In this case, the DSFgenerator 24-4 may generate the DSF of “0” instead of the DSF of “1” orgenerate the DSF of “1” instead of the DSF of “0.” In addition, as anexample, the DSF may be two bits or more rather than one bit. When theDSF is two bits, the DSF generator 24-4 shown in FIG. 4 may generatethree different 2-bit DSF, respectively, from among “00,” “01,” “10,”and “11” when the non-error signal ne, the correctable error signal ce,and the uncorrectable error signal ue are generated.

According to the example embodiments of the inventive concept, thesemiconductor memory device can generate a decoding status flagaccording to a type of an error, and a controller can perform adifferent ECC decoding operation on the basis of the decoding statusflag. Therefore, the memory system can efficiently perform an ECCdecoding operation and thus reliability can be improved.

While the embodiments of the inventive concept have been described withreference to the accompanying drawings, it should be understood by thoseskilled in the art that various modifications may be made withoutdeparting from the scope of the inventive concept and without changingessential features thereof. Therefore, all such modifications areintended to be included within the scope of the present inventiveconcept as defined in the claims.

What is claimed is:
 1. A semiconductor memory device comprising: a rowdecoder configured to decode a row address to generate a word lineselection signal; a column decoder configured to decode a column addressto generate a column selection signal; a memory cell array comprising aplurality of memory cells, one or more memory cells selected in responseto the word line selection signal and the column selection signal; andan error correcting code (ECC) decoder configured to receive first dataand a parity output from the selected memory cells of the memory cellarray and generate a syndrome based on the first data and the parity,and in response to a read operation of the semiconductor memory devicebeing performed, to generate second data and a decoding status flag(DSF) indicating a type of an error of the first data by the syndromeand to output the second data and the DSF to an external device outsideof the semiconductor memory device, wherein a number of bits of thefirst data is the same as a number of bits of the second data.
 2. Thesemiconductor memory device of claim 1, further comprising: an ECCencoder configured to receive third data from the external device, togenerate the parity, and to output fourth data and the parity to theselected memory cells when a write operation of the semiconductor memorydevice is performed, wherein a number of bits of the third data is thesame as a number of bits of the fourth data.
 3. The semiconductor memorydevice of claim 2, wherein the ECC encoder includes a parity generatorconfigured to perform an exclusive OR (XOR) operation on each of rowvectors of a first H matrix and on the third data and then perform amodulo 2 operation thereon to generate the parity, and wherein codes ofcolumn vectors of the first H matrix have different codes including “0”and “1,” that are not all “0,” and a minimum Hamming distance betweenthe codes of the first H matrix is three.
 4. The semiconductor memorydevice of claim 1, wherein the ECC decoder is configured to: output thefirst data as the second data when the syndrome indicates a non-error,correct a corresponding bit of the first data and the parity and thenoutput the corrected data as the second data when the syndrome indicatesa correctable error, and generate the DSF having a first state when thesyndrome indicates the non-error or the correctable error and a secondstate when the syndrome indicates an uncorrectable error.
 5. Thesemiconductor memory device of claim 4, wherein the second data and theDSF are output to the outside of the semiconductor memory device inseries or in parallel when the read operation is performed.
 6. Thesemiconductor memory device of claim 1, wherein the ECC decoderincludes: a syndrome generator configured to perform an XOR operation oneach of row vectors of a second H matrix, and the first data and theparity and then perform a modulo 2 operation thereon to generate apredetermined number of bits of syndrome; an error detector configuredto detect a non-error, a correctable error, or an uncorrectable errorusing the syndrome; an error position detector configured to detect aposition of the row vector of the second H matrix in which the syndromeis present to generate error position information when the correctableerror is detected; an error corrector configured to correct errors ofthe first data and the parity on the basis of the error positioninformation when the correctable error is detected; and a DSF generatorconfigured to generate the DSF of a first state when the non-error orthe correctable error is detected and generate the DSF of a second statewhen the uncorrectable error is detected.
 7. The semiconductor memorydevice of claim 6, wherein codes of column vectors of the second Hmatrix have different codes including “0” and “1,” that are not all “0,”and a minimum Hamming distance between the codes of the second H matrixis three.
 8. A controller comprising: an error correcting code (ECC)decoder configured to: perform an ECC decoding operation selected fromamong a plurality of ECC decoding operations on first data applied froman external device outside of the controller in response to a decodingstatus flag (DSF) applied from the external device and indicating a typeof an error of the first data, and generate second data and an errorsignal by performing the selected ECC decoding operation, wherein thefirst data and the DSF are provided from an outside of the controller,and wherein a number of bits of the first data is the same as a numberof bits of the second data.
 9. The controller of claim 8, wherein theECC decoder comprises: a first ECC decoding unit configured to perform afirst ECC decoding operation in response to the DSF of a first state;and a second ECC decoding unit configured to perform a second ECCdecoding operation in response to the DSF of a second state, wherein thefirst ECC decoding operation is an error detection operation, andwherein the second ECC decoding operation is an error correction anddetection operation.
 10. The controller of claim 9, wherein the firstECC decoding unit is configured to receive the first data, to generate afirst predetermined number of bits of first syndrome, and detect thatthe first syndrome indicates a non-error or a 3-bit or less error,wherein the second ECC decoding unit is configured to receive the firstdata, to generate the first predetermined number of bits of secondsyndrome, and to detect that the second syndrome indicates a non-erroror a 2-bit or less error, wherein, when the second syndrome indicatesthe non-error, the second ECC decoding unit transmits data excluding aparity with a predetermined number of bits included in the first data,and wherein, when the second syndrome indicates the 2-bit or less error,the second ECC decoding unit detects an error position of the first datato generate error position information using the second syndrome,corrects an error of the first data using the error positioninformation, and then transmits corrected data excluding the parity. 11.The controller of claim 10, wherein the first ECC decoding unitcomprises: a first syndrome generator configured to perform an exclusiveOR (XOR) operation on each of row vectors of a first H matrix and thefirst data and then perform a modulo 2 operation thereon to generate thefirst syndrome; and a first error detector configured to detect thenon-error or the 3-bit or less error using the first syndrome.
 12. Thecontroller of claim 11, wherein the second ECC decoding unit comprises:a second syndrome generator configured to perform an XOR operation oneach of row vectors of a second H matrix and the first data and thenperform a modulo 2 operation thereon to generate the first predeterminednumber of bits of second syndrome; a second error detector configured todetect the non-error or the 2-bit or less error using the secondsyndrome; an error position detector configured to detect a position ofthe row vector of the second H matrix in which the second syndrome ispresent to generate error position information when the 2-bit or lesserror is detected; and an error corrector configured to correct an errorof the first data on the basis of the error position information whenthe 2-bit or less error is detected.
 13. The controller of claim 12,wherein codes of column vectors of the first H matrix and the second Hmatrix have different codes including “0” and “1,” that are not all “0,”and a minimum Hamming distance between the codes of the first H matrixand a minimum Hamming distance between the codes of the second H matrixare four.
 14. The controller of claim 8, wherein the ECC decodercomprises: a syndrome generator configured to perform an exclusive OR(XOR) operation on each of row vectors of an H matrix and the first dataand then perform a modulo 2 operation thereon to generate apredetermined number of bits of syndrome; an error detector configuredto detect a non-error or a 3-bit or less error using the syndrome; anerror position detector configured to detect a position of the rowvector of the H matrix in which the syndrome is present to generateerror position information when the 3-bit or less error is detected inresponse to the DSF; and an error corrector configured to correct anerror of the first data on the basis of the error position informationwhen the 3-bit or less error is detected in response to the DSF.
 15. Thecontroller of claim 8, further comprising: a data processing unitconfigured to perform a data processing operation by receiving thesecond data and the error signal.
 16. A memory system comprising: asemiconductor memory device comprising: a row decoder configured todecode a row address to generate a word line selection signal; a columndecoder configured to decode a column address to generate a columnselection signal; a memory cell array comprising a plurality of memorycells, one or more memory cells are selected in response to the wordline selection signal and the column selection signal; and a first errorcorrecting code (ECC) decoder configured to: perform a first ECCdecoding operation by receiving first data and a parity output fromselected memory cells of the memory cell array, generate a syndromebased on the first data and the parity, generate second data byperforming the first ECC decoding operation, and generate a decodingstatus flag (DSF) indicating a type of an error of the first data by thesyndrome when a read operation of the semiconductor memory device isperformed; and a controller configured to control the semiconductormemory device, the controller comprising: a second ECC decoderconfigured to perform an ECC decoding operation selected from among aplurality of ECC decoding operations on the second data applied from thesemiconductor memory device in response to the DSF applied from thesemiconductor memory device.
 17. The memory system of claim 16, whereinthe first ECC decoder outputs the first data as the second data when thesyndrome indicates a non-error, when the syndrome indicates acorrectable error, corrects a corresponding bit of the first data andthe parity and then outputs the corrected data, and generates the DSFhaving a first state when the syndrome indicates the non-error or thecorrectable error and a second state when the syndrome indicates anuncorrectable error.
 18. The memory system of claim 17, wherein thesemiconductor memory device outputs the second data and the DSF to thecontroller in series or in parallel when the read operation isperformed.
 19. The memory system of claim 16, wherein the second ECCdecoder comprises: a first ECC decoding unit configured to perform asecond ECC decoding operation in response to the DSF of a first state;and a second ECC decoding unit configured to perform a third ECCdecoding operation in response to the DSF of a second state, wherein thesecond ECC decoding operation is an error detection operation, and thethird ECC decoding operation is an error correction and detectionoperation.
 20. The memory system of claim 18, wherein the second ECCdecoder comprises: a syndrome generator configured to perform anexclusive OR (XOR) operation on each of row vectors of an H matrix andthe second data and then perform a modulo 2 operation thereon togenerate a predetermined number of bits of syndrome; an error detectorconfigured to detect the non-error or a 3-bit or less error using thesyndrome; an error position detector configured to detect a position ofthe row vector of the H matrix in which the syndrome is present togenerate error position information when a 3-bit or less error isdetected in response to the DSF; and an error corrector configured tocorrect an error of the second data on the basis of the error positioninformation in response to the DSF when the 3-bit or less error isdetected, wherein codes of column vectors of the H matrix have differentcodes including “0” and “1,” that are not all “0,” and a minimum Hammingdistance between the codes of the H matrix is three.